The use of programmable synthesizers in communication systems, more specifically cellular radiotelephone systems, is well known. As these cellular radiotelephone systems develop, however, the circuit complexity and cost is continuously increasing. More advanced cellular radiotelephone systems, for example, time-division multiple access (TDMA) cellular radiotelephone systems and code-division multiple access (CDMA) cellular radiotelephone systems require radio transceivers (a combination transmitter/receiver) which incorporate frequency agile programmable synthesizers. Since transceivers in these TDMA and CDMA systems are limited in their agility by the lock-time of the programmable synthesizer, an easy and efficient alternative to frequency agility is to provide multiple programmable synthesizers per transceiver.
Typically, for each programmable synthesizer, three programming lines are used: CLOCK, DATA, and LATCH ENABLE (or CHIP SELECT). For each additional programmable synthesizer used, additional programming lines, or line groups, are normally required. However, as the number of programmable synthesizers increases, so does the circuit complexity for interfacing between adjacent microprocessors and these programmable synthesizers.
Thus, a need exists for an apparatus and method which allows for the addition of programmable synthesizers in a transceiver while mitigating circuit complexity.